The timing of memory circuitry can critically affect its performance and power consumption. Memory manufacturers have incorporated self-time circuitry into the internal memory circuitry to control timing independently of externally generated clock signals. The self-time circuitry controls the timing for accessing and pre-charging the memory cells.
To ensure robust memory operations, memory read and write margins must be met across all process, voltage and temperature (PVT) conditions and memory configurations. Self-time circuitry tracks memory operations for given instance sizes and PVT conditions, and automatically turns off internal operations of the memory upon completion of the operations to save power. Memory performance, design margins, and robustness are dependent upon the effectiveness of self-time circuitry.
Modern process technology continues to scale down spatial dimensions of memory devices. The confined spatial dimensions increase statistical variations and interconnect resistance. Interconnect RC delay becomes a significantly contributor of overall delay. Dependent upon PVT conditions, varying contributions from gate delays and RC delays present more challenges to the design of self-time circuitry.
Conventional self-time circuitry does not effectively track process corners variations in gate versus parasitic RC delays, hence functional failures may occur at faster process corners and sluggish performance at slower process corners. To ensure sufficient read and write margins at fast process corners, some self-time circuitry is delayed which results in further performance degradation at slower process corner.
Furthermore, conventional self-time circuitry is ineffective for dual-rail memory devices. Dual-rail memory architecture separates the core voltage of memory cells from the periphery voltage of peripheral circuits in the memory device. This separation allows the memory cells to have a stable voltage within a safe voltage range while the periphery voltage may be significantly lowered to reduce leakage current in the peripheral circuits. The periphery voltage can be varied to optimize between performance and power as per system requirements. Conventional self-time circuitry for dual-rail memory either provides surplus read and write margins, or insufficient margins which result in read or write failures. Therefore, there is a need for improving the self-time mechanism in a dual-rail memory device to optimize performance and power consumption.